Hybrid Check Node Architectures for NB-LDPC Decoders

An Approximate Hardware Check Node for $\\lambda$-min-based LDPC Decoders

In this paper, iterative decoding using Belief Propagation λ-min decoding algorithm is considered. In this algorithm check nodes use only the λ lowest-magnitude messages thus simplifying the hardware complexity and reducing memory usage. A parallel-input architecture is proposed for the check node. We focus on the determination of the sought minima in a parallel fashion. Novel simplified circui...

Bubble check: a simplified algorithm for elementary check node processing in extended min-sum non-binary LDPC decoders

High-throughput LDPC decoders

A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design—namely LDPC code design, decoding algorithm, and decoder architecture. First, the interconnect complexity problem of current decoder ...

Resource efficient LDPC decoders for multimedia communication

Achieving high image quality is an important aspect in an increasing number of wireless multimedia applications. These applications require resource efficient error correction hardware to detect and correct errors introduced by the communication channel. This paper presents an innovative flexible architecture for error correction using Low-Density Parity-Check (LDPC) codes. The proposed partial...

Low Complexity, Flexible LDPC Decoders

The design and implementation of a flexible LDPC decoder able to cope with different codes, is gathering an increasing interest in the scientific community. Roughly speaking, a flexible decoder exhibits the remarkable ability of being able to decode different codes resorting to the same hardware. In this paper we present a novel decoder architecture specifically devised to present an high flexi...